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I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability
ISL33001, ISL33002, ISL33003
The ISL33001, ISL33002, ISL33003 2-Channel Bus Buffers provide the necessary buffering for extending the bus capacitance beyond the 400pF maximum specified by the I2C specification. In addition, the ISL33001, ISL33002, ISL33003 feature rise time accelerator circuitry to reduce power consumption from passive bus pull-up resistors and improve data-rate performance. All devices also include hot swap circuitry to prevent corruption of the data and clock lines when I2C devices are plugged into a live backplane and level translation for mixed supply voltage applications. The ISL33001, ISL33002, ISL33003 operates at supply voltages from +2.3V to +5.5V at a temperature range of -40C to +85C.
ISL33001, ISL33002, ISL33003
Features
* 2 Channel I2C Compatible Bi-Directional Buffer * +2.3VDC to +5.5VDC Supply Range * >400kHz Operation * Bus Capacitance Buffering * Rise Time Accelerators * Hot-Swapping Capability * 6kV Class 3 HBM ESD Protection On All Pins * 12kV HBM ESD Protection on SDA/SCL Pins * Enable Pin (ISL33001 and ISL33003) * Logic Level Translation (ISL33002 and ISL33003) * READY Logic Pin (ISL33001) * Accelerator Disable Pin (ISL33002) * Pb-Free (RoHS Compliant) 8 Ld SOIC (ISL33001 only), 8 Ld TDFN (3mmx3mm) and 8 Ld MSOP packages * Low Quiescent Current . . . . . . . . . . . . . 2.2mA typ * Low Shutdown Current . . . . . . . . . . . . . . 0.5A typ
Summary of Features
PART LEVEL ENABLE READY ACCELERATOR NUMBER TRANSLATION PIN PIN DISABLE ISL33001 ISL33002 ISL33003 No Yes Yes Yes No Yes Yes No No No Yes No
Applications*(see page 15)
* I2C Bus Extender and Capacitance Buffering * Server Racks for Telecom, Datacom, and Computer Servers * Desktop Computers * Hot-Swap Board Insertion and Bus Isolation
Related Literature* (see page 15)
* AN1543, "ISL33001EVAL1Z, ISL33002EVAL1Z, ISL33003EVAL1Z Evaluation Board Manual"
Typical Operating Circuit
VCC1 +3.3V +5.0V VCC2
Bus Accelerator Performance
100kHz I2C BUS WITH 2.7k PULL-UP RESISTOR AND 400pF BUS CAPACITANCE WITHOUT BUFFER
C
BACK PLANE I2C DEVICE A I2C DEVICE B GND VOLTAGE (1V/DIV) SDA ISL33003 SCL
SDA SCL EN
WITH BUFFER
TIME (2s/DIV)
September 30, 2010 FN7560.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL33001, ISL33002, ISL33003
Ordering Information
PART NUMBER (Notes 1, 2, 3) ISL33001IRTZ ISL33001IRT2Z ISL33001IBZ ISL33001IUZ ISL33002IRTZ ISL33002IRT2Z ISL33002IUZ ISL33003IRTZ ISL33003IRT2Z ISL33003IUZ ISL33001MSOPEVAL1Z ISL33002MSOPEVAL1Z ISL33003MSOPEVAL1Z NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL33001, ISL33002, ISL33003. For more information on MSL please see techbrief TB363. PART MARKING 3001 01R2 33001 IBZ 33001 3002 02R2 33002 3003 03R2 33003 ISL33001 Evaluation Board ISL33002 Evaluation Board ISL33003 Evaluation Board TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-free) 8 Ld TDFN (0.65mm Pitch) 8 Ld TDFN (0.5mm Pitch) 8 Ld SOIC 8 Ld MSOP 8 Ld TDFN (0.65mm Pitch) 8 Ld TDFN (0.5mm Pitch) 8 Ld MSOP 8 Ld TDFN (0.65mm Pitch) 8 Ld TDFN (0.5mm Pitch) 8 Ld MSOP PKG. DWG. # L8.3x3A L8.3x3H M8.15 M8.118 L8.3x3A L8.3x3H M8.118 L8.3x3A L8.3x3H M8.118
Pin Configurations
ISL33001 (8 LD TDFN) TOP VIEW ISL33001 (8 LD SOIC, MSOP) TOP VIEW
VCC1 SDA_OUT SDA_IN
EN 1 SCL_OUT 2 SCL_IN 3 GND 4
8 7 6 5
VCC1 SDA_OUT SDA_IN READY
EN 1 SCL_OUT 2 SCL_IN 3
8 7 6
PAD
GND 4
5 READY
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Pin Configurations
ISL33002 (8 LD TDFN) TOP VIEW
VCC2 1 SCL_OUT 2 SCL_IN 3 GND 4
(Continued) ISL33002 (8 LD MSOP) TOP VIEW
VCC2 1 SCL_OUT 2 SCL_IN 3 GND 4 VCC1
8 7 6 5
VCC1 SDA_OUT SDA_IN ACC
8
PAD
7 SDA_OUT 6 SDA_IN 5 ACC
ISL33003 (8 LD TDFN) TOP VIEW
ISL33003 (8 LD MSOP) TOP VIEW
VCC2 1 SCL_OUT 2 PAD SCL_IN 3 GND 4
8 VCC1 7 SDA_OUT 6 SDA_IN 5 EN
VCC2 1 SCL_OUT 2 SCL_IN 3 GND 4
8 7 6 5
VCC1 SDA_OUT SDA_IN EN
Pin Descriptions
NAME VCC1 VCC2 ISL33002, ISL33003 NOTES PIN NUMBER 8 1 FUNCTION VCC1 power supply, +2.3V to +5.5V. Decouple VCC1 to ground with a high frequency 0.01F to 0.1F capacitor. VCC2 power supply, +2.3V to +5.5V. Decouple VCC2 to ground with a high frequency 0.01F to 0.1F capacitor. In level shifting applications, SDA_OUT and SCL_OUT logic thresholds are referenced to VCC2 supply levels. Connect pull-up resistors on these pins to VCC2. Device Ground Pin Buffer Enable Pin. Logic "0" disables the device. Logic "1" enables the device. Logic threshold referenced to VCC1. Buffer Active `Ready' Logic Output. When buffer is active, READY is high impedance. When buffer is inactive, READY is low impedance to ground. Rise Time Accelerator Enable Pin. Logic "0" disables the accelerator. Logic "1" enables the accelerator. Logic threshold referenced to VCC1. Data I/O Pins
GND EN ISL33001 ISL33003 READY ACC SDA_IN SDA_OUT SCL_IN SCL_OUT PAD Thermal Pad; TDFN only ISL33001 only ISL33002 only
4 1 5 5 5 6 7 3 2
Clock I/O Pins
Thermal pad should be connected to ground or float.
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FN7560.2 September 30, 2010
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Absolute Maximum Ratings
(All voltages referenced to GND) VCC1, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V SDA_IN, SCL_IN . . . . . . . . . . . . . -0.3V to +(VCC1 + 0.3)V SDA_OUT, SCL_OUT . . . . . . . . . . . -0.3V to +(VCC2 + 0.3)V ENABLE, READY, ACC . . . . . . . . . . -0.3V to +(VCC1 + 0.3)V Maximum Sink Current (SDA and SCL Pins). . . . . . . . . 20mA Maximum Sink Current (READY pin) . . . . . . . . . . . . . . . 7mA Latch-Up Tested per JESD78, Level 2, Class A . . . . . . . 85C ESD Ratings. . . . . . . . . . See "ESD PROTECTION" on page 5 Thermal Resistance JA (C/W) JC (C/W) 8 Ld TDFN Package (Notes 5, 6) . . . 47 4 (0.50mm Pitch) 8 Ld TDFN Package (Notes 5, 6) . . . 48 6 (0.65mm Pitch) 8 Ld MSOP Package (Notes 4, 7) . . . 151 50 8 Ld SOIC Package (Notes 4, 7). . . . 120 56 Maximum Storage Temperature Range . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersi.com/pbfree/Pb-FreeReflow.asp
Thermal Information
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . -40C to +85C VCC1 and VCC2 Supply Voltage Range . . . . . +2.3V to +5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB7379 for details. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 6. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 7. For JC, the "case temp" location is taken at the package top center.
Electrical Specifications
VEN = VCC1, VCC1 = +2.3V to +5.5V, VCC2 = +2.3V to +5.5V, unless otherwise noted (Note 8). Boldface limits apply over the operating temperature range, -40C to +85C. CONDITIONS TEMP MIN (C) (Note 9) TYP MAX (Note 9) UNITS
PARAMETER POWER SUPPLIES VCC1 Supply Range VCC2 Supply Range Supply Current from VCC1 Supply Current from VCC2 VCC1 Shut-down Supply Current
SYMBOL
VCC1 VCC2 ICC1 ISL33002 and ISL33003 VCC1 = 5.5V; ISL33001 only (Note 11) VCC1 = VCC2 = 5.5V; ISL33002 and ISL33003 (Note 11) ICC2 ISHDN1 VCC2 = VCC = 5.5V; ISL33002 and ISL33003 (Note 11) VCC1 = 5.5V, VEN = GND; ISL33001 only VCC1 = VCC2 = 5.5V, VEN = GND; ISL33003 only ISHDN2 VCC1 = VCC2 = 5.5V, VEN = GND, ISL33003 only
Full Full Full Full Full Full Full Full
2.3 2.3 -
2.1 2.0 0.22 0.5 0.05 0.06
5.5 5.5 4.0 3.0 0.6 -
V V mA mA mA A A A
VCC2 Shut-down Supply Current START-UP CIRCUITRY Precharge Circuitry Voltage Enable High Threshold Voltage Enable Low Threshold Voltage Enable Pin Input Current
VPRE VEN_H VEN_L IEN
SDA and SCL pins floating
Full +25 +25
0.8
-
1 0.5*VCC 0.5*VCC 0.1
1.2 0.7*VCC 1
V V V A
0.3*VCC -1
Enable from 0V to VCC1; ISL33001 and ISL33003
Full
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Electrical Specifications
VEN = VCC1, VCC1 = +2.3V to +5.5V, VCC2 = +2.3V to +5.5V, unless otherwise noted (Note 8). Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) CONDITIONS ISL33001 and ISL33003 (Note 10) ISL33001 and ISL33003 (Figure 1) (Figure 2, Note 12) ISL33001 only ISL33001 only (Note 10) ISL33001 only (Note 10) TEMP MIN (C) (Note 9) +25 +25 Full +25 +25 +25 Full 50 -1 TYP 10 86 83 0.1 10 10 MAX (Note 9) UNITS 150 1 0.4 ns s s A ns ns V
PARAMETER Enable Delay, On-Off Enable Delay, Off-On Bus Idle Time Ready Pin OFF State Leakage Current Ready Delay, On-Off Ready Delay, Off-On Ready Output Low Voltage
SYMBOL tEN-HL tEN-LH tIDLE IOFF tREADY-HL tREADY-LH
VOL_READY VCC1 = +2.5V, IPULLUP = 3mA; ISL33001 only
RISE-TIME ACCELERATORS Transient Accelerator Current Accelerator Enable Threshold Accelerator Disable Threshold Accelerator Pin Input Current Accelerator Delay, On-Off ESD PROTECTION SDA, SCL I/O Pins All Pins Human Body Model, SDA and SCL pins to ground only (JESD22-A114) Machine Model (JESD22-A115) Class 3 HBM ESD (JESD22-A114) INPUT-OUTPUT CONNECTIONS Input Low Threshold Input-Output Offset Voltage Output Low Voltage VIL VOS VCC1 = VCC2, 10k to VCC1 on SDA and SCL pins VCC1 = 3.3V, 10k to VCC1 on SDA and SCL pins, VINPUT = 0.2V; VCC2 = 3.3V, ISL33002 and ISL33003 (Figure 3) VCC1 = 2.7V, VINPUT = 0V, ISINK = 3mA on SDA/SCL pins; VCC2 = 2.7V, ISL33002 and ISL33003 (Figure 4) (Figure 23) +25 Full 0 0.3*VCC1 50 150 V mV +25 +25 +25 12 400 6 kV V kV ITRAN_ACC VCC1 = 2.7V, VCC2 = 2.7V; (ACC = 0.7*VCC1 for ISL33002 only) (Figure 6) ISL33002 only ISL33002 only ISL33002 only ISL33002 only (Note 10) +25 5 mA
VACC_EN VACC_DIS IACC tPDOFF
+25 +25 +25 +25
-
0.5*VCC1 0.7*VCC1
-
V V A ns
0.3*VCC1 0.5*VCC1 -1 0.1 10
1 -
VOL
Full
-
-
0.4
V
Buffer SDA and SCL Pins Input Capacitance Input Leakage Current
CIN
+25
-
10
-
pF
ILEAK
SDA and SCL pins = VCC1 = 5.5V; VCC2 = 5.5V, ISL33002 and ISL33003
Full
-5
0.1
5
A
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FN7560.2 September 30, 2010
ISL33001, ISL33002, ISL33003
Electrical Specifications
VEN = VCC1, VCC1 = +2.3V to +5.5V, VCC2 = +2.3V to +5.5V, unless otherwise noted (Note 8). Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) CONDITIONS TEMP MIN (C) (Note 9) TYP MAX (Note 9) UNITS
PARAMETER
SYMBOL
TIMING CHARACTERISTICS SCL/SDA Propagation Delay High to Low SCL/SDA Propagation Delay Low to High NOTES: 8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 9. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. Typical value determined by design simulations. Parameter not tested. 11. Buffer is in the connected state. 12. ISL33002 and ISL33003 limits established by characterization. Not production tested. tPHL CLOAD = 100pF, 2.7k to VCC1 on SDA and SCL pins, VCC1 = 3.3V; VCC2 = 3.3V, ISL33002 and ISL33003 (Figure 5) CLOAD = 100pF, 2.7k to VCC1 on SDA and SCL pins, VCC1 = 3.3V; VCC2 = 3.3V, ISL33002 and ISL33003 (Figure 5) +25 0 27 100 ns
tPLH
+25
0
2
26
ns
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FN7560.2 September 30, 2010
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Test Circuits and Waveforms
- SDA and SCL pins connected to VCC - Enable Delay Time Measured on ISL33001 only - ISL33003 performance inferred from ISL33001 - VSDA_IN = VSDA_OUT = VSCL_OUT = VEN = VCC - EN Logic High for t > Enable Delay, tEN_LH prior to SCL_IN transition - Bus Idle Time Measured on ISL33001 only - ISL33002 and ISL33003 performance inferred from ISL33001 VCC VEN 0.5 * VCC VSCL_IN 0V VCC VREADY 0V 0.5 * VCC VREADY 0V 0.5VCC
VCC
0V
VCC
0.5VCC
tEN-LH
tIDLE
FIGURE 1. ENABLE DELAY TIME
FIGURE 2. BUS IDLE TIME
+3.3V
10k SCL_OUT 10k SCL_IN VIN 0.2V GND
VCC1
10k SDA_OUT SDA_IN VIN 0.2V
10k
SCL_IN OR SDA_IN
0.2V
SCL_OUT OR SDA_OUT
VO
VOS = VO - 0.2V
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. INPUT TO OUTPUT OFFSET VOLTAGE
+2.7V
900 SCL_OUT 900 SCL_IN GND 0V
VCC1
900 SDA_OUT SDA_IN
900
VCC1 VOL VCC1
SCL_OUT
0V SDA_OUT VOL
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. OUTPUT LOW VOLTAGE
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Test Circuits and Waveforms (Continued)
+3.3V SCL_IN OR SDA_IN 2.7k SCL_OUT 2.7k SCL_IN GND VIN 100pF 100pF 100pF 100pF VIN *tPLH *tPHL SDA_IN VCC1 2.7k SDA_OUT SCL_OUT OR SDA_OUT 2.7k
*Propagation delay measured between 50% of VCC1
FIGURE 5A. TEST CIRCUIT
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. PROPAGATION DELAY
IACC = CV/t VCC1 2.7k 2.7k 2.7k 10k SDA_OUT SDA_IN GND
*V X
VCC1
*V X
100k SCL_OUT SCL_IN 2nF
10k SCL_OUT SCL_IN
10k VCC1 SDA_OUT SDA_IN GND
*V < V X CC1
10k
VCC1
(See Figure 20)
FIGURE 6. ACCELERATOR CURRENT TEST CIRCUIT
FIGURE 7. ACCELERATOR PULSE WIDTH TEST CIRCUIT
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FN7560.2 September 30, 2010
ISL33001, ISL33002, ISL33003
SDA_IN
U1 M2 M1 U2
SDA_OUT
RISE TIME ACCELERATOR
READY ISL33001 only M5
LOGIC CONTROL START-UP CIRCUITRY VCC1 EN ISL33001 and ISL33003 VCC2 ISL33002 and ISL33003 PRECHARGE CIRCUIT ACC ISL33002 only
SCL_IN
U3 M4 M3 U4
SCL_OUT
FIGURE 8. CIRCUIT BLOCK DIAGRAM
Application Information
The ISL33001, ISL33002, ISL33003 ICs are 2-Wire Bidirectional Bus Buffers designed to drive heavy capacitive loads in open-drain/open-collector systems. The ISL33001, ISL33002, ISL33003 incorporate rise time accelerator circuitry that improves the rise time for systems that use a passive pull-up resistor for logic HIGH. These devices also feature hot swapping circuitry for applications that require hot insertion of boards into a host system (i.e., servers racks and I/O card modules). The ISL33001 features a logic output flag (READY) that signals the status of the buffer and an EN pin to enable or disable the buffer. The ISL33002 features two separate supply pins for voltage level shifting on the I/O pins and a logic input to disable the rise time accelerator circuitry. The ISL33003 features an EN pin and the level shifting functionality.
With careful choosing of components, driving a bus with the I2C specified maximum bus capacitance of 400pF at 400kHz data rate is possible.
Start-Up Sequencing and Hot Swap Circuitry
The ISL33001, ISL33002, ISL33003 buffers contain undervoltage lock out (UVLO) circuitry that prevents operation of the buffer until the IC receives the proper supply voltage. For VCC1 and VCC2, this voltage is approximately 1.8V on the rising edge of the supply voltage. Externally driven signals at the SDA/SCL pins are ignored until the device supply voltage is above 1.8V. This prevents communication errors on the bus until the device is properly powered up. The UVLO circuitry is also triggered on the falling edge when the supply voltage drops below 1.7V. Once the IC comes out of the UVLO state, the buffer will remain disconnected until it detects a valid connection state. A valid connection state is either a BUS IDLE condition (see Figure 2) or a STOP BIT condition (a rising edge on SDA_IN when SCL_IN is high) along with the SCL_OUT and SDA_OUT pins being logic high. Note - For the ISL33001 and ISL33003 with EN pins, after coming out of UVLO, there will be an additional delay from the enable circuitry if the EN pin voltage is not rising at the same time as the supply pins (see Figure 1) before a valid connection state can be established.
I2C and SMBUS Compatibility
The ISL33001, ISL33002, ISL33003 ICs are I2C and SMBUS compatible devices, designed to work in open-drain/open-collector bus environments. The ICs support both clock stretching and bus arbitration on the SDA and SCL pins. They are designed to operate from DC to more than 400kHz, supporting Fast Mode data rates of the I2C specification. In addition, the buffer rise time accelerators are designed to increase the capacitive drive capability of the bus. 9
FN7560.2 September 30, 2010
ISL33001, ISL33002, ISL33003
Coming out of UVLO but prior to a valid connection state, the SDA and SCL pins are pre-charged to 1V to allow hot insertion. Because the bus at any time can be between 0V and VCC, pre-charging the I/O pins to 1V reduces the maximum differential voltage from the buffer I/O pin and the active bus. The pre-charge circuitry reduces system disturbance when the IC is hot plugged into a live back plane that may have the bus communicating with other devices. Note - For ISL33001 and ISL33003 with EN pins, the pre-charge circuitry is active only after coming out of UVLO and having the device enabled. typically 40mV. Reducing the pull-up resistor values increases the sink current and increases the output voltage of the buffer for a given input low voltage (Figures 15, 16, 17, 18).
Rise Time Accelerators
The ISL33001, ISL33002, ISL33003 buffer rise time accelerators on the SDA/SCL pins improve the transient performance of the system. Heavy load capacitance or weak pull-up resistors on an Open-Drain bus cause the rise time to be excessively long, which leads to data errors or reduced data rate performance. The rise time accelerators are only active on the low to high transitions and provide an active constant current source to slew the voltage on the pin quickly (Figure 19). The rise time accelerators are triggered immediately after the buffer release threshold (approximately 30% of VCC) on both sides of the buffer is crossed. Once triggered, the accelerators are active for a defined pulse width (Figure 20) with the current source turning off as it approaches the supply voltage.
Connection Circuitry
Once a valid connection condition is met, the buffer is active and the input stage of the SDA/SCL pins is controlled by external drivers. The output of the buffer will follow the input of the buffer. The directionality of the IN/OUT pins are not exclusive (bi-directional operation) and functionally behave identical to each other. Being a two channel buffer, the SDA and SCL pins also behave identically. In addition, the SDA and SCL portions of the buffer are independent from each other. The SDA pins can be driven in one direction while the SCL pins can be driven opposite. Refer to Figure 8 for the operation of the bi-directional buffer. When the input stage of the buffer on one side is driven low by an external device, the output of the buffer drives an open-drain transistor to pull the `output' pin low. The `output' pin will continue to be held low by the transistor until the external driver on the `input' releases the bus. To prevent the buffer from entering a latched condition where both internal transistors are actively pulling the I/O pins low, the buffer is designed to be active in only one direction. The buffer logic circuitry senses which input stage is being externally driven low and sets that buffer to be the active one. For example, referring to Figure 8, if SDA_OUT is externally driven low, buffer U2 will be active and buffer U1 is inactive. M1 is turned on to drive SDA_IN low, effectively buffering the signal from SDA_OUT to SDA_IN. The low signal at the input of U1 will not turn M2 on because U1 remains inactive, preventing a latch condition.
Enable Pin (ISL33001 and ISL33003)
When driven high, the enable pin puts the buffer into its normal operating state. After power-up, EN high will activate the bus pre-charge circuitry and wait for a valid connection state to enable the buffer and the accelerator circuitry. Driving the EN pin low disables the accelerators, disables the buffer so that signals on one side of the buffer will be isolated from the other side, disables the pre-charge circuit and places the device in a low power shutdown state.
READY Logic Pin (ISL33001 Only)
The READY pin is a digital output flag for signaling the status of the buffer. The pin is the drain of an Open-Drain NMOS. Connect a resistor from the READY pin to VCC1 to provide the high pull-up. The recommended value is 10k. When the buffer is disabled by having the EN pin low or if the start-up sequencing is not complete, the READY pin will be pulled low by the NMOS. When the buffer has the EN pin high and a valid connection state is made at the SDA/SCL pins, the READY pin will be pulled high by the pull-up resistor. The READY pin is capable of sinking 3mA when pulled low while maintaining a voltage of less than 0.4V.
Buffer Output Low and Offset Voltage
By design, when a logic input low voltage is forced on the input of the buffer, the output of the buffer will have an input to output offset voltage. The output voltage of the buffer is determined by Equation 1:
V OUT = V IN + V OS + [ V CC R PULL-UP x R ON ] (EQ. 1)
ACC Accelerator Pin (ISL33002 Only)
The ACC logic pin controls the rise time accelerator circuitry of the buffer. When ACC is driven high, the accelerators are enabled and will be triggered when crossing the buffer release threshold. When ACC is driven low, the accelerators are disabled. For lightly loaded buses, having the accelerators active may cause ringing or noise on the rising edge transition. Disabling the accelerators will have the buffers continue
Where VOS is the buffer internal offset voltage, RPull-Up is the pull up resistance on the SDA/SCL pin to VCC and RON is the ON resistance of the buffer's internal NMOS pull-down device. The last term of the equation is the additional voltage drop developed by sink current and the internal resistance of the transistor. The VOS of the buffer can be determined by Figures 17, 18 and is
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ISL33001, ISL33002, ISL33003
to perform level shifting with the VCC1 and VCC2 supplies and provide capacitance buffering. propagation delay of the buffer, there will be additional delay from the different capacitive loading of the buffer. Figures 21 and 22 show how the propagation delay from high to low, tPHL, is affected by VCC and capacitive loading. The buffer's propagation delay times for rising and falling edge signals must be taken into consideration for the timing requirements of the system. SETUP and HOLD times may need to be adjusted to take into account excessively long propagation delay times caused by heavy bus capacitances.
Propagation Delays
On a low to high transition, the rising edge signal is determined by the bus pull-up resistor, load capacitance, and the accelerator current from the ISL33001, ISL33002, ISL33003 buffer. Prior to the accelerators becoming active, the buffer is connected and the output voltage will track the input of the buffer. When the accelerators activate the buffer connection is released and the signal on each side of the buffer rises independently. The accelerator current on both sides of the buffer will be equal. If the pull-up resistance on both sides of the buffer are also equal, then differences in the rise time will be proportional to the difference in capacitive loading on the two sides. Because the signals on each side of the buffer rise independently, the propagation delay can be positive or negative. If the input side rises slowly relative to the output (i.e., heavy capacitive loading on the input and light load on the output) then the propagation delay tPLH is negative. If the output side rises slowly relative to the input, tPLH is positive. For high to low transitions, there is a finite propagation delay through the buffer from the time an external low on the input drives the NMOS output low. This propagation delay will always be positive because the buffer connect threshold on the falling edge is below the measurement points of the delay. In addition to the
Pull-Up Resistor Selection
While the ISL33001, ISL33002, ISL33003 2-Channel buffers are designed to improve the rise time of the bus in passive pull-up systems, proper selection of the pull-up resistor is critical for system operation when a buffer is used. For a bus that is operating normally without active rise time circuitry, using the ISL33001, ISL33002, ISL33003 buffer will allow larger pull-up resistor values to reduce sink currents when the bus is driving low. However, choose a pull-up resistor value of no larger than 20k regardless of the bus capacitance seen on the SDA/SCL lines. The Bus Idle or Stop Bit condition requires valid logic high voltages to give a valid connection state. Pull-up resistor values 20k or smaller are recommended to overcome the typical 150k impedance of the pre-charge circuitry, delivering valid high levels.
Typical Performance Curves
2.4 2.3 2.2 2.1 ICC1 (mA) 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 2.0 2.5 3.0 3.5 4.0 4.5 VCC1 (V) 5.0 5.5 T = +85C T = +25C T = -40C
CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25C; Unless Otherwise Specified.
600 550 500 450 ICC1 (nA) 400 350 300 250 200 150 6.0 100 2.0 2.5 3.0 3.5 4.0 VCC1 (V) 4.5 5.0 5.5 6.0 T = +85C T = +25C
FIGURE 9. ICC1 ENABLED CURRENT vs VCC1 (ISL33001)
FIGURE 10. ICC1 DISABLED CURRENT vs VCC1 (ISL33001)
11
FN7560.2 September 30, 2010
ISL33001, ISL33002, ISL33003
Typical Performance Curves
2.4 2.3 2.2 2.1 ICC1 (mA) 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 2.0 2.5 3.0 3.5 4.0 VCC1 (V) 4.5 5.0 5.5 T = +85C T = -40C VCC2 = 5.5V
CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25C; Unless Otherwise Specified. (Continued)
60 VCC2 = 5.5V 50 40 30 20 10 0 2.0 T = +25C T = +85C
6.0
ICC1 (nA)
T = +25C
2.5
3.0
3.5
4.0 VCC1 (V)
4.5
5.0
5.5
6.0
FIGURE 11. ICC1 ENABLED CURRENT vs VCC1 (ISL33002 AND ISL33003)
FIGURE 12. ICC1 DISABLED CURRENT vs VCC1 (ISL33003)
0.24 0.22 0.20 ICC2 (mA) 0.18 0.16 0.14 0.12 0.10 2.0 VCC1 = 5.5V T = -40C
T = +25C
60 50 40 30 20 10 0 VCC1 = 5.5V
ICC2 (nA)
T = +85C
T = +85C
T = +25C
2.5
3.0
3.5
4.0 4.5 VCC2 (V)
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC2 (V)
FIGURE 13. ICC2 ENABLED CURRENT vs VCC2 (ISL33002 AND ISL33003)
FIGURE 14. ICC2 DISABLED CURRENT vs VCC2 (ISL33003)
120 VCC = 2.3V 100 80 VOL (mV) 60 40 20 VIN = 0V 0 0 1 2 3 4 5 6 7 8 9 10 11 VCC = 4.5V VCC = 2.7V
120 100 T = +85C 80 60 40 20 0 VCC = 3.3V VIN = 0V 0 1 2 3 4 T = +25C
T = -40C
VOL (mV)
IOL (mA)
5 7 6 IOL (mA)
8
9
10
11
FIGURE 15. SDA/SCL OUTPUT LOW VOLTAGE vs SINK CURRENT vs VCC
FIGURE 16. SDA/SCL OUTPUT LOW VOLTAGE vs SINK CURRENT vs TEMPERATURE
12
FN7560.2 September 30, 2010
ISL33001, ISL33002, ISL33003
Typical Performance Curves
100 90 80 70 VOS (mV) VCC = 5.5V
CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25C; Unless Otherwise Specified. (Continued)
100 90 80 70 VOS (mV) 60 50 40 30 20 VCC = 3.3V VIN = 0.2V 1 2 3 4 5 6 7 8 9 10 11 T = +85C T = +25C T = -40C
60 50 40 30 20 10 0 0 VIN = 0.2V 1 2 3 4 6 7 IOL (mA) 5 8 9 10 11 VCC = 2.3V VCC = 3.3V
10 0 0
IOL (mA)
FIGURE 17. INPUT TO OUTPUT OFFSET VOLTAGE vs SINK CURRENT vs VCC
FIGURE 18. INPUT TO OUTPUT OFFSET VOLTAGE vs SINK CURRENT vs TEMPERATURE
ACCELERATOR PULSE WIDTH (ns)
12 ACCELERATOR CURRENT (mA) 11 10 9 8 7 6 5 4 3 2.0 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 6.0 T = +25C T = +85C T = -40C
800 700
(See Figure 7)
T = +25C 600 500 400 300 200 2.0 T = +85C T = -40C
2.5
3.0
3.5
4.0 4.5 VCC (V)
5.0
5.5
6.0
FIGURE 19. ACCELERATOR PULL-UP CURRENT vs VCC
FIGURE 20. ACCELERATOR PULSE WIDTH vs VCC
50 T = +85C PROPAGATION DELAY (ns) 40 T = +25C 30
RPULL-UP = 2.7k CIN = 10pF COUT = 100pF PROPAGATION DELAY (ns)
50 T = +85C 40
30 T = +25C 20 T = -40C 10 VCC = 3.3V RPULL-UP = 10k CIN = 50pF 100 200 300 400 500 600 700 800 900 COUT (pF)
20
T = -40C
10
0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 0
VCC (V)
FIGURE 21. PROPAGATION DELAY H-L vs VCC
FIGURE 22. PROPAGATION DELAY H-L vs COUT
13
FN7560.2 September 30, 2010
ISL33001, ISL33002, ISL33003
Typical Performance Curves
12 11 CAPACITANCE (pF) 10
CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25C; Unless Otherwise Specified. (Continued)
VCC = 2.3V VCC = 3.3V VCC = 5.5V
9 8 7 6 -30
-10
10
30
50
70
90
TEMPERATURE (C)
FIGURE 23. SDA/SCL PIN CAPACITANCE vs TEMPERATURE vs VCC
Die Characteristics
SUBSTRATE AND TDFN THERMAL PAD POTENTIAL (POWERED UP): GND PROCESS: 0.25m CMOS
14
FN7560.2 September 30, 2010
ISL33001, ISL33002, ISL33003
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 9/13/10 4/30/10 REVISION FN7560.2 FN7560.1 CHANGE Added SOIC package information to datasheet for ISL33001. Changed typical value of "Supply Current from VCC1" on page 4 for ISL33001 only from 2.2mA to 2.1mA. Changed typical value of "Input-Output Offset Voltage" on page 5 from 100mV to 50mV. Initial Release.
3/18/10
FN7560.0
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL33001, ISL33002, ISL33003 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
15
FN7560.2 September 30, 2010
ISL33001, ISL33002, ISL33003
Package Outline Drawing
L8.3x3H
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) Rev 0, 2/08
2.38 1.50 REF 3.00 6 PIN 1 INDEX AREA A PIN #1 INDEX AREA 6 X 0.50 6 B 1 4 8 X 0.40
2.20 3.00 1.64
(4X)
0.15 8 5 0.10 M C A B 8 X 0.25
TOP VIEW
BOTTOM VIEW
( 2.38 ) SEE DETAIL "X"
0 .80 MAX
0.10 C
C
BASE PLANE
SEATING PLANE 0.08 C
2 . 80
( 2 .20 )
( 1.64 )
SIDE VIEW
C 8X 0.60
0.2 REF
0 . 00 MIN. 0 . 05 MAX. ( 8X 0.25 )
DETAIL "X"
( 6X 0 . 5 )
NOTES:
TYPICAL RECOMMENDED LAND PATTERN
1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Lead width dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
16
FN7560.2 September 30, 2010
ISL33001, ISL33002, ISL33003
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10
( 2.30) 3.00 A B ( 1.95)
( 8X 0.50) 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW PIN 1 (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN (1.50) ( 2.90 )
SEE DETAIL "X" 2X 1.950 6X 0.65 PIN #1 INDEX AREA 6 1.50 0.10 1 SIDE VIEW 0.75 0.05 0.10 C C 0.08 C
8 8X 0.30 0.10 2.30 0.10 BOTTOM VIEW 8X 0.30 0.05 0.10 M C A B 4
C
0 . 2 REF
5
0 . 02 NOM. 0 . 05 MAX. DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
2. 3. 4.
17
FN7560.2 September 30, 2010
ISL33001, ISL33002, ISL33003
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10
5 3.00.05 A 8 D DETAIL "X"
1.10 MAX
SIDE VIEW 2 4.90.15
0.09 - 0.20
3.00.05 5
PIN# 1 ID 1 2 B 0.65 BSC TOP VIEW
0.95 REF
GAUGE PLANE
0.25
0.55 0.15 H 0.85010 DETAIL "X" C SEATING PLANE 0.25 - 0.036 0.08 M C A-B D SIDE VIEW 1 0.10 0.05 0.10 C
33
(5.80) (4.40) (3.00) NOTES: 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only.
(0.65) (0.40) (1.40)
TYPICAL RECOMMENDED LAND PATTERN
18
FN7560.2 September 30, 2010
ISL33001, ISL33002, ISL33003 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN7560.2 September 30, 2010

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